This invention relates to circuitry and methods for use in interfacing data between two clock regimes that may have somewhat different frequencies.
An example of a context in which the invention can be used is the reception of a high-speed serial data signal by a programmable logic device (“PLD”) integrated circuit. The clock rate of the incoming data signal may be somewhat different from the clock rate that needs to be used on most of the PLD for processing the data. High-speed serial interface (“HSSI”) circuitry may be provided on the PLD for performing such tasks as (1) recovering clock and data signals from the incoming data signal, (2) converting the data from serial to parallel form, and (3) buffering the parallel data between the clock rate that it had when received and the clock rate at which it will be further processed by the PLD. Typical parts of the buffering circuitry include (1) first-in/first-out (“FIFO”) memory circuitry for storing successive incoming data words at the incoming clock rate and subsequently outputting those words at the PLD processing rate, (2) character insertion circuitry for inserting dummy characters into the FIFO output data if and when reading from the FIFO gets too close to writing to the FIFO, and (3) character deletion circuitry for deleting dummy characters from the FIFO output if and when writing to the FIFO gets too far ahead of reading from the FIFO.
Because some circuitry (such as PLD circuitry) is intended to be relatively general-purpose circuitry, it is typical for such circuitry to be designed to accommodate both the possibility that the read clock may be faster than the write clock and the possibility that the write clock may be faster than the read clock. This may lead to a design for the interface circuitry that has a relatively high latency (i.e., a relatively long delay between the reception of data by the interface circuitry and output of the same data from the interface circuitry). A reason for this characteristic of typical prior systems is that those systems do not attempt to determine which of the read and write clocks is faster in a particular situation, or to adapt the configuration of the interface circuitry depending on the relative speeds of those clocks.